Guide to Computer Processor Architecture A RISCV Approach, with HighLevel Synthesis

The book presents a succession of RISC-V processor implementationsin increasing difficulty (non pipelined, pipelined, deeply pipelined,multithreaded, multicore).Each implementation is shown as an HLS (High Level Synthesis) codein C++ which can really be synthesized and tested on an FPGA baseddevelopment board (such a board can be freely obtained from the XilinxUniversity Program targeting the university professors).The book can be useful for three reasons. First, it is a novel way tointroduce computer architecture. The codes given can serve as labsfor a processor architecture course. Second, the book content is basedon the RISC-V Instruction Set Architecture, which is an open-sourcemachine language promised to become the machine language to be taught,replacing DLX and MIPS. Third, all the designs are implemented throughthe High Level Synthesis, a tool which is able to translate a C program intoan IP (Intellectual Property). Hence, the book can serve to engineers willingto implement processors on FPGA and to researchers willing to developRISC-V based hardware simulators.